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lt1175 1 1175ff typical application features description 500ma negative low dropout micropower regulator the lt ? 1175 is a negative micropower low dropout regulator. it features 45a quiescent current, dropping to 10a in shutdown. a new reference ampli? er topology gives precision dc characteristics along with the ability to maintain good loop stability with an extremely wide range of output capacitors. very low dropout voltage and high ef? ciency are obtained with a unique power transistor anti-saturation design. adjustable and ? xed 5v versions are available. several new features make the lt1175 very user-friendly. the shdn pin can interface directly to either positive or negative logic levels. current limit is user-selectable at 200ma, 400ma, 600ma and 800ma. the output can be forced to reverse voltage without damage or latchup. un- like some earlier designs, the increase in quiescent current during a dropout condition is actively limited. the lt1175 has complete blowout protection with current limiting, power limiting and thermal shutdown. special attention was given to the problem of high temperature operation with micropower operating currents, preventing output voltage rise under no-load conditions. the lt1175 is available in 8-pin pdip and so packages, 3-lead sot- 223 as well as 5-pin surface mount dd and through-hole to-220 packages. the 8-pin so package is specially constructed for low thermal resistance. typical lt1175 connection applications n operating current: 45a n adjustable current limit n low voltage linear dropout characteristics n stable with wide range of output capacitors n shutdown current: 10a n positive or negative shutdown logic n fixed 5v and adjustable versions n tolerates reverse output voltage n available in 8-pin pdip and so packages, 3-lead sot-223, 5-pin surface mount dd and through-hole to-220 packages n analog systems n modems n instrumentation n a/d and d/a converters n interface drivers n battery-powered systems l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. minimum input-to-output voltage c in * *c in is needed only if regulator is more than 6" from input supply capacitor. see applications information section for details c out 0.1f C5v up to 500ma Cv in shdn gnd lt1175-5 sense output 1175 ta01 i lim4 i lim2 v in + + output current (a) 0 input-to-output voltage (v) 1.0 0.8 0.6 0.4 0.2 0 0.2 0.4 0.5 1175 ta02 0.1 0.3 0.6 0.7 t j = 25c i lim2 , i lim4 tied to v in
lt1175 2 1175ff absolute maximum ratings input voltage (transient 1 sec, note 12) ...................25v input voltage (continuous) .......................................20v input-to-output differential voltage (note 13) ..........20v 5v sense pin (with respect to gnd pin) ......... 2v, C10v adj sense pin (with respect to output pin) ...................20v, C0.5v 5v sense pin (with respect to output pin) ......................20v, C7v pin configuration output reverse voltage ..............................................2v shdn pin to gnd pin voltage (note 3) ........ 13.5v, C20v shdn pin to v in pin voltage .............................30v, C5v operating junction temperature range (note 2) lt1175c ................................................. 0c to 125c lt1175i .............................................. C40c to 125c lt1175mp .......................................... C55c to 125c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec)................... 300c 1 2 3 4 8 7 6 5 top view v in i lim2 output sense v in i lim4 shd n gnd n8 package 8-lead pdip ja = 80c/w to 120c/w depending on pc board layout shdn gnd v in sense output q package 5-lead plastic dd-pak front view tab is v in 5 4 3 2 1 ja = 27c/w to 60c/w depending on pc mounting. see data sheet for details 3 2 1 front view tab is v in gnd v in output st package 3-lead plastic sot-223 ja = 50c/w with backplane and 10cm 2 topside land soldered to tab 1 2 3 4 8 7 6 5 top view s8 package 8-lead plastic so v in i lim2 output sense v in i lim4 shd n gnd ja = 60c/w to 100c/w depending on pc board layout pins 1, 8 are internally connected to die attach paddle for heat sinking. electrical contact can be made to either pin. for best thermal resistance, pins 1, 8 should be connected to an expanded land that is over an internal or backside plane. see applications information t package 5-lead plastic to-220 front view 5 4 3 2 1 shdn gnd v in sense output tab is v in ja = 50c/w, jc = 5c/w (note 1)
lt1175 3 1175ff order information lead free finish tape and reel part marking* package description temperature range lt1175cn8#pbf lt1175cn8#trpbf lt1175cn8 8-lead plastic dip 0c to 125c lt1175cn8-5#pbf lt1175cn8-5#trpbf lt1175cn8-5 8-lead plastic dip 0c to 125c lt1175cs8#pbf lt1175cs8#trpbf 1175 8-lead plastic so 0c to 125c lt1175cs8-5#pbf lt1175cs8-5#trpbf 11755 8-lead plastic so 0c to 125c lt1175cst-5#pbf lt1175cst-5#trpbf 11755 3-lead plastic sot-223 0c to 125c lt1175cq#pbf lt1175cq#trpbf lt1175cq 5-lead plastic dd-pak 0c to 125c lt1175cq-5#pbf lt1175cq-5#trpbf lt1175cq-5 5-lead plastic dd-pak 0c to 125c lt1175ct#pbf lt1175ct#trpbf lt1175ct 5-lead plastic to-220 0c to 125c lt1175ct-5#pbf lt1175ct-5#trpbf lt1175ct-5 5-lead plastic to-220 0c to 125c lt1175in8#pbf lt1175in8#trpbf lt1175in8 8-lead plastic dip C40c to 125c lt1175in8-5#pbf lt1175in8-5#trpbf lt1175in8-5 8-lead plastic dip C40c to 125c lt1175is8#pbf lt1175is8#trpbf 1175i 8-lead plastic so C40c to 125c lt1175is8-5#pbf lt1175is8-5#trpbf 1175i5 8-lead plastic so C40c to 125c lt1175ist-5#pbf lt1175ist-5#trpbf 1175i5 3-lead plastic sot-223 C40c to 125c lt1175iq#pbf lt1175iq#trpbf lt1175iq 5-lead plastic dd-pak C40c to 125c lt1175iq-5#pbf lt1175iq-5#trpbf lt1175iq-5 5-lead plastic dd-pak C40c to 125c lt1175it#pbf lt1175it#trpbf lt1175it 5-lead plastic to-220 C40c to 125c lt1175it-5#pbf lt1175it-5#trpbf lt1175it-5 5-lead plastic to-220 C40c to 125c lt1175mps8#pbf lt1175mps8#trpbf 1175mp 8-lead plastic so C55c to 125c lt1175mps8-5#pbf lt1175mps8-5#trpbf 175mp5 8-lead plastic so C55c to 125c lt1175mpq#pbf lt1175mpq#trpbf lt1175mpq 5-lead plastic dd-pak C55c to 125c lt1175mpq-5#pbf lt1175mpq-5#trpbf lt1175mpq-5 5-lead plastic dd-pak C55c to 125c lead based finish tape and reel part marking* package description temperature range lt1175cn8 lt1175cn8#tr lt1175cn8 8-lead plastic dip 0c to 125c lt1175cn8-5 lt1175cn8-5#tr lt1175cn8-5 8-lead plastic dip 0c to 125c lt1175cs8 lt1175cs8#tr 1175 8-lead plastic so 0c to 125c lt1175cs8-5 lt1175cs8-5#tr 11755 8-lead plastic so 0c to 125c lt1175cst-5 lt1175cst-5#tr 11755 3-lead plastic sot-223 0c to 125c lt1175cq lt1175cq#tr lt1175cq 5-lead plastic dd-pak 0c to 125c lt1175cq-5 lt1175cq-5#tr lt1175cq-5 5-lead plastic dd-pak 0c to 125c lt1175ct lt1175ct#tr lt1175ct 5-lead plastic to-220 0c to 125c lt1175ct-5 lt1175ct-5#tr lt1175ct-5 5-lead plastic to-220 0c to 125c lt1175in8 lt1175in8#tr lt1175in8 8-lead plastic dip C40c to 125c lt1175in8-5 lt1175in8-5#tr lt1175in8-5 8-lead plastic dip C40c to 125c lt1175is8 lt1175is8#tr 1175i 8-lead plastic so C40c to 125c lt1175is8-5 lt1175is8-5#tr 1175i5 8-lead plastic so C40c to 125c lt1175ist-5 lt1175ist-5#tr 1175i5 3-lead plastic sot-223 C40c to 125c lt1175iq lt1175iq#tr lt1175iq 5-lead plastic dd-pak C40c to 125c lt1175iq-5 lt1175iq-5#tr lt1175iq-5 5-lead plastic dd-pak C40c to 125c
lt1175 4 1175ff order information lead free finish tape and reel part marking* package description temperature range lt1175it lt1175it#tr lt1175it 5-lead plastic to-220 C40c to 125c lt1175it-5 lt1175it-5#tr lt1175it-5 5-lead plastic to-220 C40c to 125c lt1175mps8 lt1175mps8#tr 1175mp 8-lead plastic so C55c to 125c lt1175mps8-5 lt1175mps8-5#tr 175mp5 8-lead plastic so C55c to 125c lt1175mpq lt1175mpq#tr lt1175mpq 5-lead plastic dd-pak C55c to 125c lt1175mpq-5 lt1175mpq-5#tr lt1175mpq-5 5-lead plastic dd-pak C55c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ electrical characteristics the l denotes speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v out = 5v, v in = 7v, i out = 0, v shdn = 3v, i lim2 and i lim4 tied to v in . to avoid confusion with min and max as applied to negative voltages, all voltages are shown as absolute values except where polarity is not obvious. parameter conditions min typ max units feedback sense voltage adjustable part fixed 5v part 3.743 4.93 3.8 5.0 3.857 5.075 v v output voltage initial accuracy adjustable, measured at 3.8v sense fixed 5v 0.5 0.5 1.5 1.5 % % output voltage accuracy (all conditions) v in C v out = 1v to v in = 20v, i out = 0a to 500ma p = 0 to p max , t j = t min to t max (note 4) l 1.5 2.5 % quiescent input supply current v in C v out 12v l 45 65 80 a a gnd pin current increase with load (note 5) l 10 20 a/ma input supply current in shutdown v shdn = 0v l 10 20 25 a a shutdown thresholds (note 10) either polarity on shdn pin (c-, i-grades) either polarity on shdn pin (mp-grade) l l 0.8 0.8 2.5 2.6 v v shdn pin current (note 3) v shdn = 0v to 10v (flows into pin) v shdn = C15v to 0v (flows into pin) l 4 1 8 4 a a output bleed current in shutdown (note 7) v out = 0v, v in = 15v l 0.1 1 1 5 a a sense pin input current (adjustable part only, current flows out of pin) (fixed voltage only, current flows out of pin) l l 75 12 150 20 na a dropout voltage (note 8) i out = 25ma i out = 100ma i out = 500ma i lim2 open, i out = 300ma i lim4 open, i out = 200ma i lim2 , i lim4 open, i out = 100ma l l l l l l 0.1 0.18 0.5 0.33 0.3 0.26 0.2 0.26 0.7 0.5 0.45 0.45 v v v v v v
lt1175 5 1175ff note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt1175 regulators are tested and speci? ed under pulse load conditions such that t j t a . the lt1175c is 100% production tested at t a = 25c. performance at 0c and 125c is assured by design, characterization and correlation with statistical process controls. the lt1175i is guaranteed over the full C40c to 125c operating junction temperature range. the lt1175mp is 100% tested and guaranteed over the C55c to 125c operating junction temperature range. note 3: shdn pin maximum positive voltage is 30v with respect to Cv in and 13.5v with respect to gnd. maximum negative voltage is C20v with respect to gnd and C5v with respect to Cv in . note 4: p max = 1.5w for 8-pin packages, and 6w for 5-pin packages. this power level holds only for input-to-output voltages up to 12v, beyond which internal power limiting may reduce power. see guaranteed current limit curve in typical performance characteristics section. note that all conditions must be met. note 5: gnd pin current increases because of power transistor base drive. at low input-to-output voltages (<1v) where the power transistor is in saturation, gnd pin current will be slightly higher. see typical performance characteristics. note 6: with i load = 0, at t j > 125c, power transistor leakage could increase higher than the 10a to 25a drawn by the output divider or ? xed voltage sense pin, causing the output to rise above the regulated value. to prevent this condition, an internal active pull-up will automatically turn on, but supply current will increase. note 7: this is the current required to pull the output voltage to within 1v of ground during shutdown. note 8: dropout voltage is measured by setting the input voltage equal to the normal regulated output voltage and measuring the difference between v in and v out . for currents between 100ma and 500ma, with both i lim pins tied to v in , maximum dropout can be calculated from v do = 0.15 + 1.1 (i out ). note 9: thermal regulation is a change in the output voltage caused by die temperature gradients, so it is proportional to chip power dissipation. temperature gradients reach ? nal value in less than 100ms. output voltage changes after 100ms are due to absolute die temperature changes and reference voltage temperature coef? cient. note 10: the lower limit of 0.8v is guaranteed to keep the regulator in shutdown. the upper limit of 2.5v is guaranteed to keep the regulator active. either polarity may be used, referenced to gnd pin. note 11: load and line regulation are measured on a pulse basis with pulse width of 20ms or less to keep chip temperature constant. dc regulation will be affected by thermal regulation (note 8) and chip temperature changes. load regulation speci? cation also holds for currents up to the speci? ed current limit when i lim2 or i lim4 are left open. note 12: current limit is reduced for input-to-output voltage above 12v. see the graph in typical performance characteristics for guaranteed limits above 12v. note 13: operating at very large input-to-output differential voltages (>15v) with load currents less than 5ma requires an output capacitor with an esr greater than 1 to prevent low level output oscillations. electrical characteristics the l denotes speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v out = 5v, v in = 7v, i out = 0, v shdn = 3v, i lim2 and i lim4 tied to v in . to avoid confusion with min and max as applied to negative voltages, all voltages are shown as absolute values except where polarity is not obvious. parameter conditions min typ max units current limit (note 12) v in C v out = 1v to 12v i lim2 open i lim4 open i lim2 , i lim4 open l l l l 520 390 260 130 800 600 400 200 1300 975 650 325 ma ma ma ma line regulation (note 11) v in C v out = 1v to v in = 20v l 0.003 0.015 %/v load regulation (note 6, 11) i out = 0ma to 500ma l 0.1 0.35 % thermal regulation p = 0 to p max (notes 4, 9) 5-pin packages 8-pin packages 0.04 0.1 0.1 0.2 %/w %/w output voltage temperature drift t j = 25c to t jmin , or 25c to t jmax 0.25 1.25 %
lt1175 6 1175ff typical performance characteristics typical current limit characteristics guaranteed current limit output voltage temperature drift minimum input-to-output voltage minimum input-to-output voltage sense bias current (adjustable part) input-to-output differential voltage (v) 0 current (a) 1.0 0.8 0.6 0.4 0.2 0 20 1175 g01 5 10 15 25 i lim2 , i lim4 tied to v in i lim2 , i lim4 open i lim4 tied to v in i lim2 tied to v in current limit changes only slightly with temperature so curves are representative of all temperatures input-to-output differential voltage (v) 0 current (a) 0.6 0.5 0.4 0.3 0.2 0.1 0 5101520 1175 g02 25 curves repre- sent minimum guaranteed limits at all temperatures i lim2 , i lim4 open i lim4 tied to v in i lim2 tied to v in i lim2 , i lim4 tied to v in junction temperature (c) C50 voltage (v) 5.05 5.00 4.95 3.84 3.80 3.76 0 50 75 1175 g03 C25 25 100 125 output fixed 5v part feedback voltage adjustable part output current (a) 0 input-to-output voltage (v) 1.0 0.8 0.6 0.4 0.2 0 0.2 0.4 0.5 1175 g04 0.1 0.3 0.6 0.7 t j = 25c v in reduced until output voltage drops 1% i lim2 , i lim4 open i lim2 , i lim4 tied to v in i lim4 tied to v in i lim2 tied to v in output current (a) 0 input-to-output voltage (v) 1.0 0.8 0.6 0.4 0.2 0 0.2 0.4 0.5 1175 g05 0.1 0.3 0.6 0.7 v in reduced until output voltage drops 1%. i lim2 , i lim4 tied to v in t j = 125c t j = C55c t j = 25c temperature (c) C50 current (na) 100 80 60 40 20 0 0 50 75 1175 g06 C25 25 100 125
lt1175 7 1175ff typical performance characteristics gnd pin current ripple rejection shutdown input current shutdown thresholds shdn pin characteristics input voltage (v) 0 input current (a) 25 20 15 10 5 0 20 1175 g07 5 10 15 25 t j = 125c t j = C55c t j = 25c temperature (c) C50 threshold (v) 2.5 2.0 1.5 1.0 0.5 0 0 50 25 75 1175 g08 C25 100 125 positive threshold negative threshold device is off below threshold shutdown to ground voltage (v) C25 C20 C10 0 pin current (a) 15 10 5 0 C5 C10 15 1175 g09 C15 C5 10 20 5 25 v in = 25v characteristics do not change significantly with temperature, so a single curve is shown. positive current flows into shdn pin if shdn pin is negative with respect to input voltage and input voltage is less than 15v, negative breakover point will be about 8v below Cv in output current (a) 0 ground pin current (ma) 20 16 12 8 4 0 0.2 0.4 0.3 0.5 1175 g10 0.1 0.6 0.7 power transistor in dropout t j = C55c t j = 25c v in C v out 3v t j = 25c v in C v out = 2v t j = 25c frequency (hz) rejection (db) 100 80 60 40 20 0 10 1k 10k 1m 100 100k v out = 12v (adjustable) i out = 100ma v in C v out = 2v c out = 1f tant 1175 g11 ripple rejection is relatively independent of input voltage and load for currents between 25ma and 500ma. larger output capacitors do not improve rejection for frequencies below 50khz. at very light loads, rejection will improve with larger output capacitors v out = 12v (adjustable) with 0.1f across divider resistor v out = 5v (fixed)
lt1175 8 1175ff pin functions v in (pins 1, 8/pin 3, tab/pin 2, tab/pins 1, 8/pin 3, tab): power is supplied to the device through this pin. a bypass capacitor is required on this pin if the device is more than six inches away from the main ? lter capacitor. in general, the impedance of a battery rises with frequency, so it is advisable to include a bypass capacitor in battery-powered circuits. a 1f or larger tantalum capacitor is suggested for all applications, but if low esr capacitors such as ceramic or ? lm are used for the output and input capaci- tors, the input capacitor should be three times the value of the output capacitor. i lim2 , i lim4 (pins 2, 7/na/na/pins 2, 7/na): the two current limit pins are emitter sections of the power transis- tor. when left open, they ? oat several hundred millivolts above the negative input voltage. when shorted to the input voltage, they increase current limit by a minimum of 200ma for i lim2 and 400ma for i lim4 . these pins must be connected only to the input voltage, either directly or through a resistor. output (pin 3/pin 1/pin 1/pin 3/pin 1): the output pin is the collector of the npn power transistor. it can be forced to the input voltage, to ground or up to 2v positive with respect to ground without damage or latchup (see output voltage reversal in applications information section). the lt1175 has foldback current limit, so maximum current at the output pin is a function of input-to-output voltage. see typical performance characteristics. sense (pin 4/pin 2/na/pin 4/pin 2): the sense pin is used in the adjustable version to allow custom selection of output voltage, with an external divider set to generate 3.8v at the sense pin. input bias current is typically 75na ? owing out of the pin. maximum forced voltage on the sense pin is 2v and C10v with respect to gnd pin. the ? xed 5v version utilizes the sense pin to give true kelvin connections to the load or to drive an external pass transistor for higher output currents. bias current out of the 5v sense pin is approximately 12a. separating the sense and output pins also allows for a new loop compensation technique described in the applications information section. gnd (pin 5/pin 4/pin 3/pin 5/pin 4): the gnd pin has a quiescent current of 45a at zero load current, increas- ing by approximately 10a per ma of output current. at 500ma output current, gnd pin current is about 5ma. current ? ows into the gnd pin. shdn (pin 6/pin 5/na/pin 6/pin 5): the shdn pin is specially con? gured to allow it to be driven from either positive voltage logic or with negative only logic. forc- ing the shdn pin 2v either above or below the gnd pin will turn the regulator on. this makes it simple to connect directly to positive logic signals for active low shutdown. if no positive voltages are available, the shdn pin can be driven below the gnd pin to turn the regulator on. when left open, the shdn pin will default low to a regulator on condition . for all voltages below absolute maximum ratings, the shdn pin draws only a few microamperes of current (see typical performance characteristics). maximum voltage on the shdn pin is 15v, C 20v with respect to the gnd pin and 35v, C5v with respect to the negative input pin. (n8/q/st/s8/t)
lt1175 9 1175ff applications information setting output voltage the lt1175 adjustable version has a feedback sense voltage of 3.8v with a bias current of approximately 75na ? owing out of the sense pin. to avoid output voltage errors caused by this current, the output divider string (see figure 1) should draw about 25a. table 1 shows suggested resistor values for a range of output voltages. the second part of the table shows resistor values which draw only 10a of current. output voltage error caused by bias current with the lower valued resistors is about 0.4% maximum and with the higher values, about 1% maximum. a formula is also shown for calculating the resistors for any output voltage. table 1. suggested divider resistors output voltage r1 i div = 25a r2 nearest 1% r1 i div = 10a r2 nearest 1% 5v 150k 47.5k 383k 121k 6v 150k 86.6k 383k 221k 8v 150k 165k 383k 422k 10v 150k 243k 383k 619k 12v 150k 324k 383k 825k 15v 150k 442k 383k 1.13m r v i r rv v v simple formula rv v vri i desired div out out fb div 1 38 2 138 38 138 38 1 = = ? () () = ? () + () ? ? ? ? ? ? = . . . . . r2 taking sense pin bias current into account divider current note to reader: to avoid confusion when working with negative voltages (is C6v more or less than C5v?), i have decided to treat the lt1175 as if it were a positive regulator and express all voltages as positive values, both in text and in formulas. if you do the same and simply add a negative sign to the eventual answer, confusion should be avoided. please dont give me a hard time about preciseness or correctness. i have to ? eld phone calls from around the world and this is my way of dealing with a multitude of conventions. thanks for your patience. the lt1175-5 is a ? xed 5v design with the sense pin acting as a kelvin connection to the output. normally the sense pin and the output pin are connected directly together, either close to the regulator or at the remote load point. setting current limit the lt1175 uses two i lim pins to set current limit (typical) at 200ma, 400ma, 600ma or 800ma. the corresponding minimum guaranteed currents are 130ma, 260ma, 390ma and 520ma. this allows the user to select a current limit tailored to his speci? c application and prevents the situa- tion where short-circuit current is many times higher than full-load current. problems with input supply overload or excessive power dissipation in a faulted load are prevented. power limiting in the form of foldback current limit is built in and reduces current limit as a function of input-to-output voltage differential for differentials exceed ing 14v. see the graph in typical performance characteristics. the lt1175 is guaranteed to be blowout-proof regardless of current limit setting. the power limiting combined with thermal shutdown protects the device from destructive junction temperatures under all load conditions. shutdown in shutdown, the lt1175 draws only about 10a. special circuitry is used to minimize increases in shutdown cur- rent at high temperatures, but a slight increase is seen above 125c. one option not taken was to actively pull down on the output during shutdown. this means that the output will fall slowly after shutdown is initiated, at a rate determined by load current plus the 12a internal load, and the size of the output capacitor. active pull-down is figure 1. typical lt1175 adjustable connection + c in c out 0.1f v out C12v r2 825k 1% r1 383k 1% shutdown logic shdn gnd lt1175 sense output > 2v or < C2v to turn regulator on 1175 f01 i lim4 i lim2 v in +
lt1175 10 1175ff applications information normally a good thing when the regulator is used by itself, but it prevents the user from shutting down the regulator when a second power source is connected to the lt1175 output. if active output pull-down is needed in shutdown, it can be added externally with a depletion mode pfet as shown in figure 2. note that the maximum pinch-off volt- age of the pfet must be less than the positive logic high level to ensure that the device is completely off when the regulator is active. the motorola j177 device has 300 on resistance for zero gate source voltage. yet allows the power transistor to approach its theoretical saturation limit. output capacitor several new regulator design techniques are used to make the lt1175 extremely tolerant of output capacitor selection. like most low dropout designs which use a collector or drain of the power transistor to drive the output node, the lt1175 uses the output capacitor as part of the overall loop compensation. older regulators generally required the output capacitor to have a minimum value of 1f to 100f, a maximum esr (effective series resistance) of 0.1 to 1 and a minimum esr in the range of 0.03 to 0.3. these restrictions usually could be met only with good quality solid tantalum capacitors. aluminum capaci- tors have problems with high esr unless much higher values of capacitance are used (physically large). the esr of ceramic or ? lm capacitors was too low , which made the capacitance/esr zero frequency too high to maintain phase margin in the regulator. even with optimum capaci- tors, loop phase margin was very low in previous designs when output current was low. these problems led to a new design technique for the lt1175 error ampli? er and internal frequency compensation as shown in figure 3. a conventional regulator loop consists of error ampli? er a1, driver transistor q2 and power transistor q1. added to this basic loop are secondary loops generated by q3 and c f . a dc negative feedback current fed into the error ampli? er through q3 and r n causes overall loop current gain to be very low at light load currents. this is not a problem because very little gain is needed at light loads. in addition to low gain, the parasitic pole frequency at q2 base is extended by the dc feedback. the combination of these two effects dramatically improves loop phase margin at light loads and makes the loop tolerant of large esr in the output capacitor. with heavy loads, loop phase and gain are not nearly as troublesome and large negative feedback could degrade regulation. the logarithmic behavior of the base emitter voltage of q1 reduces q3 negative feedback at heavy loads to prevent poor regulation. in a conventional design, even with the nonlinear feedback, poor loop phase margin would occur at medium to heavy loads if the esr of the output capacitor fell below 0.3. minimum dropout voltage dropout voltage is the minimum voltage required between input and output to maintain proper output regulation. for older 3-terminal regulator designs, dropout voltage was typically 1.5v to 3v. the lt1175 uses a saturating power transistor design which gives much lower dropout voltage, typically 100mv at light loads and 450mv at full load. special precautions were taken to ensure that this technique does not cause quiescent supply current to be high under light load conditions. when the regulator input voltage is too low to maintain a regulated output, the pass transistor is driven hard by the error ampli? er as it tries to maintain regulation. the current drawn by the driver transistor could be tens of milliamperes even with little or no load on the output. this indeed was the case for older ic designs that did not actively limit driver current when the power transistor saturated. the lt1175 uses a new antisaturation technique that prevents high driver current, figure 2. active output pull-down during shutdown c out 0.1f Cv in q1* s d shdn gnd 3v to 5v lt1175-5 sense output 1175 f02 i lim4 i lim2 v in * motorola j177 pinch-off voltage must be less than positive logic high voltage +
lt1175 11 1175ff applications information C + lt1175 a1 3.8v r1 esr output 1175 f03 c out output gnd sense r2 r c 0.5 r lim r n c f 20pf + parasitic collector resistance power transistor negative dc feedback at light loads ac feedforward path current limit sense resistor q2 q1 v in load q3 this condition can occur with ceramic or ? lm capacitors which often have an esr under 0.1. with previous de- signs, the user was forced to add a real resistor in series with the capacitor to guarantee loop stability. the lt1175 uses a unique ac feedforward technique to eliminate this problem. c f is a conventional feedforward capacitor often used in regulators to cancel the pole formed by the output capacitor. it would normally be connected from the regulated output node to the feedback node at the r1/r2 junction or to an internal node on the ampli? er as shown. in this case, however, the capacitor is connected to the internal structure of the power transistor. r c is the unavoid- able parasitic collector resistance of the power transistor. access to the node at the bottom of r c is available only in monolithic structures where kelvin connections can be made to the npn buried collector layer. the loop now responds as if r c were in series with the output capacitor and good loop stability is achieved even with extremely low esr in the output capacitor. the end result of all this attention to loop stability is that the output capacitor used with the lt1175 can range in value from 0.1f to hundreds of microfarads, with an esr from 0 to 10. this range allows the use of ceramic, solid tantalum, aluminum and ? lm capacitors over a wide range of values. the optimum output capacitor type for the lt1175 is still solid tantalum, but there is considerable leeway in selecting the exact unit. if large load current transients are expected, larger capacitors with lower esr may be needed to control worst-case output variation during transients. if transients are not an issue, the capacitor can be chosen for small physical size, low price, etc. concerns about surge currents in tantalum capacitors are not an issue for the output capacitor because the lt1175 limits inrush current to well below the level which can cause capacitor damage. surges caused by shorting the regulator output are also not a problem because tantalum figure 3
lt1175 12 1175ff applications information capacitors do not fail during a shorting out surge, only during a charge up surge. the output capacitor should be located within several inches of the regulator. if remote sensing is used, the output capacitor can be located at the remote sense node, but the gnd pin of the regulator should also be connected to the remote site. the basic rule is to keep sense and gnd pins close to the output capacitor, regardless of where it is. operating at very large input-to-output differential volt- ages (>15v) with load currents less than 5ma requires an output capacitor with an esr greater than 1 to prevent low level output oscillations. input capacitor the lt1175 requires a separate input bypass capacitor only if the regulator is located more than six inches from the raw supply output capacitor. a 1f or larger tantalum capacitor is suggested for all applications, but if low esr capacitors such as ceramic or ? lm are used for the out- put and input capacitors, the input capacitor should be at least three times the value of the output capacitor. if a solid tantalum or aluminum electrolytic output capacitor is used, the input capacitor is very noncritical. high temperature operation the lt1175 is a micropower design with only 45a qui- escent current. this could make it perform poorly at high temperatures (>125c), where power transistor leakage might exceed the output node loading current (5a to 15a). to avoid a condition where the output voltage drifts uncontrolled high during a high temperature no-load condition, the lt1175 has an active load which turns on when the output is pulled above the nominal regulated voltage. this load absorbs power transistor leakage and maintains good regulation. there is one downside to this feature, however. if the output is pulled high deliberately, as it might be when the lt1175 is used as a backup to a slightly higher output from a primary regulator, the lt1175 will act as an unwanted load on the primary regulator. because of this, the active pull-down is deliberately weak. it can be modeled as a 2k resistor in series with an internal clamp voltage when the regulator output is being pulled high. if a 4.8v output is pulled to 5v, for instance, the load on the primary regulator would be (5v C 4.8v)/2k = 100a. this also means that if the internal pass transistor leaks 50a, the output voltage will be (50a)(2k) = 100mv high. this condition will not occur under normal operating conditions, but could occur immediately after an output short circuit had overheated the chip. thermal considerations the lt1175 is available in a special 8-pin surface mount package which has pins 1 and 8 connected to the die attach paddle. this reduces thermal resistance when pins 1 and 8 are connected to expanded copper lands on the pc board. table 2 shows thermal resistance for various combinations of copper lands and backside or internal planes. table 2 also shows thermal resistance for the 5-pin dd surface mount package and the 8-pin dip and package. table 2. package thermal resistance (c/w) land area dip st so q minimum 140 90 100 60 minimum with backplane 110 70 80 50 1cm 2 top plane with backplane 100 64 75 35 10cm 2 top plane with backplane 80 50 60 27 to calculate die temperature, maximum power dissipation or maximum input voltage, use the following formulas with correct thermal resistance numbers from table 2. for through-hole to-220 applications use ja = 50c/w without a heat sink and ja = 5c/w + heat sink thermal resistance when using a heat sink. die v v i maximum ja in out load temp=t + a ? ()() power dissipation = t max ? t a ja = t max ? t a a ja load out i v () + maximum input voltage for thermal considerations
lt1175 13 1175ff applications information t a = maximum ambient temperature t max = maximum lt1175 die temperature (125c for commercial and industrial grades) ja = lt1175 thermal resistance, junction to ambient v in = maximum continuous input voltage at maximum load current i load = maximum load current example: lt1175s8 with i load = 200ma, v out = 5v, v in = 7v, t a = 60c. maximum die temperature for the lt1175s8 is 125c. thermal resistance from table 2 is found to be 80c/w. die temperature = 60 + 80 (0.2a)(8 C 5) = 108c maximum w v power dissipation = 125 C 60 80 125 C 60 = = () += 081 80 0 2 59 . . maximum continuous input voltage (for thermal considerations) output voltage reversal the lt1175 is designed to tolerate an output voltage reversal of up to 2v. reversal might occur, for instance, if the output was shorted to a positive 5v supply. this would almost surely destroy ic devices connected to the negative output. reversal could also occur during start- up if the positive supply came up ? rst and loads were connected between the positive and negative supplies. for these reasons, it is always good design practice to add a reverse biased diode from each regulator output to ground to limit output voltage reversal . the diode should be rated to handle full negative load current for start-up situations, or the short-circuit current of the positive supply if supply-to-supply shorts must be tolerated. input voltage lower than output linear technologys positive low dropout regulators lt1121 and lt1129, will not draw large currents if the input voltage is less than the output. these devices use a lateral pnp power transistor structure that has 40v emitter base breakdown voltage. the lt1175, however, uses an npn power transistor structure that has a parasitic diode between the input and output of the regulator . reverse voltages between input and output above 1v will damage the regulator if large currents are allowed to ? ow. simply disconnecting the input source with the output held up will not cause damage even though the input-to-output voltage will become slightly reversed. high frequency ripple rejection the lt1175 will sometimes be powered from switching regulators that generate the unregulated or quasi-regulated input voltage. this voltage will contain high frequency ripple that must be rejected by the linear regulator. special care was taken with the lt1175 to maximize high frequency ripple rejection, but as with any micropower design, rejection is strongly affected by ripple frequency. the graph in the typical performance characteristics section shows 60db rejection at 1khz, but only 15db rejection at 100khz for the 5v part. photographs in figures 4a and 4b show actual output ripple waveforms with square wave and triwave input ripple. figure 4a. figure 4b. 5s/div output 20mv/div c out = 1f tant f = 50khz c out = 4.7f tant input ripple 100mv/div 1175 f04a 2s/div output 100mv/div c out = 1f tant f = 100khz c out = 4.7f tant input ripple 100mv/div 1175 f04b
lt1175 14 1175ff to estimate regulator output ripple under different conditions, the following general comments should be helpful: 1. output ripple at high frequency is only weakly affected by load current or output capacitor size for medium to heavy loads. at very light loads (<10ma), higher frequency ripple may be reduced by using larger output capacitors. 2. a feedforward capacitor across the resistor divider used with the adjustable part is effective in reducing ripple only for output voltages greater than 5v and only for frequencies less than 100khz. 3. input-to-output voltage differential has little effect on ripple rejection until the regulator actually enters a dropout condition of 0.2v to 0.6v. if ripple rejection needs to be improved, an input ? lter can be added. this ? lter can be a simple rc ? lter using a 1 to 10 resistor. a 3.3 resistor for instance, combined with a 0.3 esr solid tantalum capacitor, will give an ad- ditional 20db ripple rejection. the size of the resistor will be dictated by maximum load current. if the maximum voltage drop allowable across the resistor is v r , and maximum load current is i load , r = v r /i load . at light loads, larger resistors and smaller capacitors can be used to save space. at heavier loads an inductor may have to be used in place of the resistor. the value of the inductor can be calculated from: l esr f fil rr = () () 2 10 20 / esr = effective series resistance of ? lter capacitor. this assumes that the capacitive reactance is small com- pared to esr, a reasonable assumption for solid tantalum capacitors above 2.2f and 50khz. f = ripple frequency rr = ripple rejection ratio of ? lter in db example: esr = 1.2, f = 100khz, rr = C 25db. lh fil = ? ? ? ? ? ? ? ? = ? 12 63 10 10 34 5 25 20 . . / solid tantalum capacitors are suggested for the ? lter to keep ? lter q fairly low. this prevents unwanted ringing at the resonant frequency of the ? lter and oscillation problems with the ? lter/regulator combination. applications information
lt1175 15 1175ff package description n8 package 8-lead pdip (narrow .300 inch) (reference ltc dwg # 05-08-1510) n8 1002 .065 (1.651) typ .045 C .065 (1.143 C 1.651) .130 .005 (3.302 0.127) .020 (0.508) min .018 .003 (0.457 0.076) .120 (3.048) min 12 3 4 87 6 5 .255 .015* (6.477 0.381) .400* (10.160) max .008 C .015 (0.203 C 0.381) .300 C .325 (7.620 C 8.255) .325 +.035 C.015 +0.889 C0.381 8.255 () note: 1. dimensions are inches millimeters *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 inch (0.254mm) .100 (2.54) bsc
lt1175 16 1175ff package description q package 5-lead plastic dd pak (reference ltc dwg # 05-08-1461) q(dd5) 0502 .028 C .038 (0.711 C 0.965) typ .143 +.012 C.020 () 3.632 +0.305 C0.508 .067 (1.702) bsc .013 C .023 (0.330 C 0.584) .095 C .115 (2.413 C 2.921) .004 +.008 C.004 () 0.102 +0.203 C0.102 .050 .012 (1.270 0.305) .059 (1.499) typ .045 C .055 (1.143 C 1.397) .165 C .180 (4.191 C 4.572) .330 C .370 (8.382 C 9.398) .060 (1.524) typ .390 C .415 (9.906 C 10.541) 15 typ .420 .350 .565 .090 .042 .067 recommended solder pad layout .325 .205 .080 .565 .090 recommended solder pad layout for thicker solder paste applications .042 .067 .420 .276 .320 note: 1. dimensions in inch/(millimeter) 2. drawing not to scale .300 (7.620) .075 (1.905) .183 (4.648) .060 (1.524) .060 (1.524) .256 (6.502) bottom view of dd pak hatched area is solder plated copper heat sink
lt1175 17 1175ff package description .016 C .050 (0.406 C 1.270) .010 C .020 (0.254 C 0.508) 45 0 C 8 typ .008 C .010 (0.203 C 0.254) so8 0303 .053 C .069 (1.346 C 1.752) .014 C .019 (0.355 C 0.483) typ .004 C .010 (0.101 C 0.254) .050 (1.270) bsc 1 2 3 4 .150 C .157 (3.810 C 3.988) note 3 8 7 6 5 .189 C .197 (4.801 C 5.004) note 3 .228 C .244 (5.791 C 6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) .114 C .124 (2.90 C 3.15) .248 C .264 (6.30 C 6.71) .130 C .146 (3.30 C 3.71) .264 C .287 (6.70 C 7.30) .0905 (2.30) bsc .033 C .041 (0.84 C 1.04) .181 (4.60) bsc .024 C .033 (0.60 C 0.84) .071 (1.80) max 10 max .012 (0.31) min .0008 C .0040 (0.0203 C 0.1016) 10 C 16 .010 C .014 (0.25 C 0.36) 10 C 16 recommended solder pad layout st3 (sot-233) 0502 .129 max .059 max .059 max .181 max .039 max .248 bsc .090 bsc st package 3-lead plastic sot-223 (reference ltc dwg # 05-08-1630)
lt1175 18 1175ff package description t package 5-lead plastic to-220 (standard) (reference ltc dwg # 05-08-1421) t5 (to-220) 0801 .028 C .038 (0.711 C 0.965) .067 (1.70) .135 C .165 (3.429 C 4.191) .700 C .728 (17.78 C 18.491) .045 C .055 (1.143 C 1.397) .095 C .115 (2.413 C 2.921) .013 C .023 (0.330 C 0.584) .620 (15.75) typ .155 C .195* (3.937 C 4.953) .152 C .202 (3.861 C 5.131) .260 C .320 (6.60 C 8.13) .165 C .180 (4.191 C 4.572) .147 C .155 (3.734 C 3.937) dia .390 C .415 (9.906 C 10.541) .330 C .370 (8.382 C 9.398) .460 C .500 (11.684 C 12.700) .570 C .620 (14.478 C 15.748) .230 C .270 (5.842 C 6.858) bsc seating plane * measured at the seating plane
lt1175 19 1175ff information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number e 11/09 revised typical application. revised pin con? guration drawings and layout. updated order information. v in added and pin numbers added to pin functions. title added to table 1. revised figures 1, 2, 3, 4a and 4b. value correction in ? nal paragraph of the output capacitor section. 1 2 3 7 8 8, 9, 10, 12 11 f 7/10 added mp-grade. replaced note 2, renumbered all other notes and revised shutdown thresholds in the electrical characteristics section. updated related parts. 2C4 4, 5 20 (revision history begins at rev e)
lt1175 20 1175ff linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 1995 lt 0710 rev f ? printed in usa related parts part number description comments lt1121 150ma positive micropower low dropout regulator with shutdown sot-223, 8-lead so, to-92 packages lt1129 700ma positive micropower low dropout regulator with shutdown dd-pak, sot-223, 8-lead so, to-220, 20-lead tssop packages lt1185 3a negative low dropout regulator dd-pak, to-220 packages lt1521 300ma positive micropower low dropout regulator with shutdown sot-223, 8-lead so, 8-lead msop packages lt1529 3a positive micropower low dropout regulator with shutdown dd-pak, to-220 packages lt1964 200ma negative low dropout linear regulator 5-lead tsot-23, 8-lead (3mm 3mm) dfn packages

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